An electronic circuit is chemically and physically integrated into a substrate such as a wafer by patterning regions in the substrate and by patterning layers on the substrate. These regions and layers can be conductive for conductor and resistor fabrication, or insulative, for insulator and capacitor fabrication. They can also be of differing conductivity types, which is essential for transistor and diode fabrication. Degrees of resistance, capacitance, or conductivity are controllable, as are the physical dimensions and locations of the patterned regions and layers, making circuit integration possible. Fabrication can be quite complex and time consuming and, therefore, expensive. It is thus a continuing quest of those in the semiconductor fabrication business to reduce fabrication times and costs of such devices in order to increase profits. Any simplified processing steps or combination of processes at a single step becomes a competitive advantage.
One application where a process simplification is desirable is in the application of a photoresist layer to a substrate and, particularly, to a substrate on which an existing layer of photoresist has been formed in certain areas or on various semiconductor devices formed on the substrate. In a photoresist process, a substrate may be masked with a patterned photoresist and then etched. This is often done several times. An adhesion promoter such as hexamethyldisilazane (HMDS) may be applied in the form of a vapor prime to promote adhesion of the photoresist to the substrate.
In general, even with the use of an adhesion promoter such as (HMDS), however, it is often difficult to adhere a subsequent layer of photoresist to a layer which has been previously coated with photoresist. Such a double layer photoresist scheme may exist, for instance, for certain semiconductor implant layers where the first resist acts as an implant stop for the area beneath it, and the second layer acts as a stop for a larger area. Such a scheme may be used, for instance, for complimentary metal oxide semiconductor (CMOS) parts in order to implement an N-channel field implant mask.
In order to provide for adhesion of a subsequent photoresist layer, a number of process steps and separate pieces of equipment are required. FIG. 1 shows a representative prior art process sequence. As shown, a semiconductor wafer is initially patterned with a photoresist. The wafer is then baked to toughen or harden the photoresist. Baking is followed by a dip in solvents to soften the photoresist. The wafer is then rinsed and dried. This is followed by another bake which is not as extreme as the first bake but functions to slightly harden the photoresist after the solvent treatment. Each of these steps requires a separate piece of process equipment, each of which is common in the art. Following these steps, an adhesion promotor such as (HMDS) is applied to the wafer by vapor deposition. A second layer of photoresist layer is then applied.
The process of the invention eliminates several of these preparatory steps and pieces of equipment and allows a subsequent layer of photoresist to be applied to a wafer in a single step utilizing a single piece of equipment.